The present invention relates to a semiconductor memory device, and more particularly, to a data input buffer of a flash memory device.
Semiconductor memory devices are used for storing data. The semiconductor memory devices may be classified by various criteria. As one example, semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices according to whether they retain data even when power is interrupted. The volatile memory devices retain data when power is being supplied, but their stored data disappear when power is interrupted. Examples of the volatile memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM). On the other hand, the nonvolatile memory devices retain data even when power is interrupted. Examples of the nonvolatile memory devices include mask erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory devices. As portability of electronic devices is emphasized, the use of nonvolatile memory devices is further increasing. In particular, flash memory devices among the nonvolatile memory devices are widely used because they can store and read data in a convenient way.
Flash memory devices are generally classified into NAND flash memory devices and NOR flash memory devices. In a NOR flash memory device, one MOS transistor is connected to a word line and a bit line as a unit storage element. Like in a general DRAM, a plurality of bit lines are disposed to cross a plurality of word lines, and a plurality of MOS transistors are disposed at crossing points between the bit lines and the word lines as unit storage elements. In a NAND flash memory device, a plurality of MOS transistors are serially connected to form one string as unit storage elements for high integration. That is, a drain of a MOS transistor is connected to a source of an adjacent MOS transistor. Therefore, the NOR flash memory device has a fast read/write speed, but is disadvantageous in high integration. On the other hand, the NAND flash memory device has a slow read/write speed, but is advantageous in high integration. In recent years, the demand for high-capacity portable memory devices has significantly increased.
A data storing operation of a flash memory device includes a program operation and an erase operation. The program operation is to change a threshold voltage of a MOS transistor used as a unit storage element of the flash memory device, and the erase operation is to restore the change threshold voltage of the MOS transistor. For example, the threshold voltages of the MOS transistors where data “1” will be stored are reduced to a predetermined level, and the threshold voltages of the MOS transistors where data “0” will be stored are maintained as they are.
FIG. 1 is a block diagram illustrating a read operation of a flash memory device. The flash memory device receives a command signal and an address and outputs data through one data input/output (I/O) pad.
Referring to FIG. 1, in the read operation, a read command and an address are sequentially inputted and then data is outputted. An I/O timing of the command, the address, and the data is controlled by control signals ALE, WEB, REB, CLE and R/BB. The command and the address inputted from the outside through one data I/O pad are stored in a data input buffer. The command and the address stored in the data input buffer are transferred to a core region. A data output buffer outputs the stored data through the data I/O pad through which the command and the address have been inputted. Therefore, the data input buffer is always in an enabled state while the read command for outputting the data to the outside is executed. This causes high power consumption in the flash memory device.
FIG. 2 is a block diagram of a conventional flash memory device.
Referring to FIG. 2, the conventional flash memory device includes a data output buffer 10, an input timing controller 20, a data input buffer 30, an electrostatic discharge (ESD) protector 40, and a data input controller 50.
The data output buffer 10 stores data DOUT and outputs the stored data DOUT through a data I/O pad DQ to the outside. The ESD protector 40 protects internal circuits, e.g., the data input buffer 30 and the input timing controller 20, from electrostatic discharge inputted through the data I/O pad DQ. The data input buffer 30 latches data, address, command transferred through the data I/O pad DQ and transfers them to the input timing controller 20 in response to an enable signal EN. The data input controller 50 generates the enable signal EN for controlling an enable timing of the data input buffer 30 in response to control signals STDBY and BYTE. The control signals STDBY and BYTE are activated in a standby mode. The data input controller 50 controls the data input buffer 30 to be disabled in the standby mode. The input timing controller 20 controls setup/hold timing of data, address, and command outputted from the data input buffer 30 and transfers the controlled setup/hold timing to the core region.
FIG. 3 is a circuit diagram of the data input controller 50 illustrated in FIG. 2.
Referring to FIG. 3, the data input controller 50 includes a NAND gate ND1 configured to receive the control signals STDBY and BYTE, and inverters I1 and I2 serially connected to invert an output signal of the NAND gate ND1.
As described above, the data input buffer 30 of the conventional flash memory device is always in the turned-on state all the modes other than the standby mode. Therefore, the conventional flash memory device consumes a large amount of current while the read or write command is executed.